1. Field of the Invention
The present invention relates generally to package construction of integrated circuits. More specifically, but without limitation thereto, the present invention relates to the electrical and mechanical connection of a semiconductor die to an integrated circuit package, more specifically, a flip-chip ball grid array (FPBGA) package.
2. Description of the Prior Art
One obstacle to flip-chip technology when applied to polymer printed circuit substrates is the poor reliability of solder joints due to mismatch of the coefficients of thermal expansion of the chip, which typically has a coefficient of thermal expansion of about 3 ppm/° C.; the polymer substrate, for example, epoxy-glass, which has a coefficient of thermal expansion of about 16–26 ppm/° C.; and the solder joint, which has a coefficient of thermal expansion of about 25 ppm/° C. The mismatch in the coefficients of thermal expansion results in stress on the solder joints during thermal expansion and contraction that may cause the chip to malfunction.
The trend towards copper metallization and low-k dielectrics for 0.13 micron and smaller silicon technologies is driving the development of new packaging processes and material. In flip-chip packages, the most critical material may be the underfill material. Due to its close proximity to the inner layers of the silicon die, the underfill material influences the stress conditions at the low-K dielectric layers of the silicon. Consequently, the underlying underfill material and the processes associated with its formation play an important role in determining the reliability of the silicon in the flip-chip package.